Recently, in order to meet demands for high-speed semiconductor device, miniaturization of a wiring pattern and high level of integration, it is required to decrease an inter-wiring capacitance and realize high conductivity of wiring and high electromigration resistance. In view of the above, Copper (Cu), which has a higher electromigration resistance and a higher conductivity than those of aluminum (Al) and tungsten (W), is being used as a wiring material. As for a technique for forming a Cu wiring, there is often used a damascene method for forming a recess such as a wiring groove (trench), a connecting opening (hole) or the like in an interlayer insulation film and then filling Cu in the recess (see, e.g., Patent Document 1). As the miniaturization of the semiconductor devices advances, a parasitic capacitance of the interlayer insulation film is an important factor for improving performance of the wiring. As for the interlayer insulation film, a low-k film made of a low-k material is used.
In order to accurately form a recess in the interlayer insulation film, it is suggested to use a metal hard mask such as a Ti film or a TiN film as an etching mask (see, e.g., Patent Document 2).
Patent Document 1: Japanese Patent Application Publication No. 2002-083869
Patent Document 2: Japanese Patent Application Publication No. 2003-229482
However, in the case of manufacturing the Cu wiring, the recess is formed in the interlayer insulation film by dry etching while using the metal hard mask. If necessary, an etching residue, the hard mask or the like is removed by dry ashing. Next, wet cleaning is performed and, then, a wiring forming process is performed.
At this time, if a period of time between the dry etching and the wet cleaning or between the dry ashing and the wet cleaning is long, a film quality of the interlayer insulation film may deteriorate. Especially, in the case of using a low-k film as the interlayer insulation film, a dielectric constant is increased until the wet cleaning is started. If the film quality of the interlayer insulation film deteriorates, problems such as a decrease in reliability after next wiring formation and the like are caused.
Therefore, conventionally, it is required to strictly manage a period of time between the etching process and a next cleaning process or between the ashing process and a next cleaning process. This leads to a decrease in a yield of a product and the like.
In order to solve the above problems, it is considered to avoid contact between the interlayer insulation film and exterior air by forming a coating on the interlayer insulation film after the etching process or the ashing process. However, it is required that the coating be simply formed and easily removed before the wiring forming process, preferably before the cleaning process or during the cleaning process, so that the wiring or the like is not adversely affected. There is not yet discovered a technique that satisfies the above demands while ensuring sufficient protection.